Subject: Re: [vhdl-200x] RE: Advisory vote: simple subset of PSL
From: Evan Lavelle (email@example.com)
Date: Tue Sep 16 2003 - 00:31:11 PDT
Bailey, Stephen wrote:
> I need to ensure everyone takes a big whiff of reality.
Absolutely. Just to clarify - I had already voted 'yes' on the advisory
vote. There is no realistic alternative to having something which is
close to PSL (and I speak as a temporal 'e' user). My specific problems
are - what exactly is PSL, what is the agenda for PSL, who controls PSL,
and are we going to get into big trouble if we're not careful here?
There *is* an agenda for PSL. The FVTC based 1.01 on Sugar 2. This
turned out to be unsuitable for SystemVerilog after the OVA donation.
The FVTC was then instructed to move 1.01 towards OVA, and to produce
1.1 in the process. This is, on the face of it, of no benefit to either
VHDL or Verilog.
I say 'on the face of it' for the simple reason that I don't actually
know. I don't know PSL 1.01, and I don't know what the FVTC intends to
change to turn it into 1.1, but I do know that parts of the FVTC weren't
happy about this.
Question: can we get the benefits of PSL by referencing Sugar 2, which
is, I think, already a public standard? How much does 1.01 differ from
Sugar 2? How much does 1.01 differ from what may be in 1.1? And is
anyone in 1364 asking the same questions, or are they waiting for 1.1?
> - Do you trust that (when it comes down to it) Accellera is an honest organization that wants to do the right thing? If so, then there's not much concern that Accellera will pull the plug on PSL or its use within VHDL. The PSL designers (and, by the fact that someone other than Accellera funded their work, many EDA companies) put significant effort into making PSL usable with VHDL. Why would they want to throw that away?
Well.. sure, I believe that they want to do the right thing. However, in
this context 'the right thing' is to increase the bottom line of the
sponsors. I have no problem at all with this, and I think it's a very
laudable aim. We have to do the right thing as well, which is to ensure
that VHDL isn't sidelined. This may involve getting into bed with
SystemVerilog and OVA, but I sincerely hope that it doesn't.
> There are EDA companies that already have products supporting PSL.
Correct me if I'm wrong, but I believe that they're supporting 1.01.
> Eventually, Accellera will release PSL to the IEEE for standardization.
I wish I was so sure!
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