Subject: RE: [vhdl-200x] RE: Advisory vote: simple subset of PSL
From: Bailey, Stephen (SBailey@model.com)
Date: Mon Sep 15 2003 - 14:51:53 PDT
Hi Evan,
I need to ensure everyone takes a big whiff of reality.
FACT: The vote is an advisory vote. If the answer is no, what is the better alternative (remember, what is to be used as the basis or starting point)?
1. Adopt work done for another language with no consideration for working with VHDL, specifically, SystemVerilog Assertions (with all the FUD going on with that language war who knows if SVA will every become part of 1364)?
2. Adopt a proprietary standard (choose your acronym: Verisity's e assertions?, Synopsys's OpenVera Assertions?, Sugar, I can't remember all the donated languages that Accellera's FVTC considered, but choose any or all of them)? Is that a better starting point?
3. Dismiss all the work that has gone into the assertion languages/capabilities identified in 1 and 2 above and develop our own?
4. Delay the entire effort? For what purpose, so we are 6-12 months later than what we need to be? All I can say is that there would be many a happy camper from the Verilog world if we delay.
The reality is that just because PSL is subject to some changes, that doesn't mean that we cannot begin the task of integrating it into VHDL. (However it could mean we can't complete it -- but we aren't there yet to consider it.) Because we plan to incorporate by reference, the work is on the VHDL side and must be done no matter the final form of PSL. Do the potential changes impact the work? Maybe. But, it will definitely not trash 100% of the work done. I can't imagine it impacting more than a modest amount (20% or less) of the work and even that depends on how fast we do our work relative to how fast Accellera completes its work.
More on incorporating by reference:
- It is the most efficient way to use an existing standard, as is, within another standard. This sort of dependency has already occurred multiple times. Examples: 1164, 1076.1, 1076.2, 1076.3, 1076.4, 1076.5, 1076.6, 1364.1 and the WAVEs standard prior. Also, VITAL references SDF.
- Yes, it requires that the referring standard keep up-to-date with the reference standard. But, that is still easier than reinventing a non-standard wheel.
- Do you trust that (when it comes down to it) Accellera is an honest organization that wants to do the right thing? If so, then there's not much concern that Accellera will pull the plug on PSL or its use within VHDL. The PSL designers (and, by the fact that someone other than Accellera funded their work, many EDA companies) put significant effort into making PSL usable with VHDL. Why would they want to throw that away? There are EDA companies that already have products supporting PSL.
Eventually, Accellera will release PSL to the IEEE for standardization.
-Steve Bailey
> -----Original Message-----
> From: Evan Lavelle [mailto:eml@riverside-machines.com]
> Sent: Monday, September 15, 2003 5:51 AM
> To: vhdl-200x@eda.org
> Cc: Bailey, Stephen; 'Tom Fitzpatrick'
> Subject: Re: [vhdl-200x] RE: Advisory vote: simple subset of PSL
>
>
> Bailey, Stephen wrote:
>
> > First, neither the WG nor the IEEE requires that PSL be an
> IEEE standard. The 1.01 version of PSL was approved by the
> Accellera board as reported in the 2 June 2003 Press Release
> http://www.accellera.org/press19.html.
> >
> > Second, we have no plan or desire to duplicate or modify
> the PSL standard by physically incorporating it (duplicating
> in part or whole) into the VHDL standard. It will be
> incorporated by reference. Therefore, any Accellera (or
> IEEE, if PSL has been donated to IEEE by then) changes to PSL
> up to a cut-off point determined by when we (the WG) decide
> it is OK to ballot will be automatically included. This is
> entirely in compliance to Accellera's "Declaration of
> Conditions of Use Without License Accellera Property
> Specification Language" http://www.accellera.org/pslconditions.html.
>
> I'm not keen on this idea of incorporating by reference, for
> a couple of
> reasons:
>
> 1 Licensing
> ------------
>
> As various people have pointed out, PSL is evolving. What
> exactly is the
> 'PSL' referred to in
> <http://www.accellera.org/pslconditions.html>? Is
> it possible that Accellera could decide that some earlier version of
> what we consider to be PSL isn't actually the 'real' PSL? Is
> it possible
> that Accellera could change the licence conditions in the
> future, or for
> a future version of PSL? And, of course, we can't rely on a licence
> statement of the website - is there any other legal documentation
> covering licensing?
>
> 2 Versions
> ----------
>
> Clearly, you can't reference the 'current' version of PSL -
> you have to
> reference a specific document which covers a specific version of PSL.
> But, this gives us a problem - future versions of PSL could
> evolve in a
> way that is dictated by the requirements of SystemVerilog,
> rather than
> VHDL or Verilog.
>
> Does IBM have a public specification for 1.01? If so, would this be a
> suitable alternative?
>
> Evan
>
>
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