Subject: Re: [vhdl-200x] [Fwd: Multi-dimentional arrays in components using generics]
From: Jim Lewis (Jim@synthworks.com)
Date: Sat Jul 12 2003 - 20:58:19 PDT
If proposal 2 below can be impemented and does not
conflict with the big picture of DTA (potential OO
extensions), perhaps we should do it as a fast track
item.
Issue:
Designer needs parameterizable two dimensional array on ports
to solve the following type of problem:
COMPONENT Reduce is
generic
( Width : integer;
Depth : integer
);
port
( D_IN : IN array(Depth -1 downto 0) of
std_logic_vector(Width-1 downto 0);
Q : OUT array(Depth -2 downto 0) of
std_logic_vector(Width-2 downto 0);
);
end COMPONENT;
We have other types of problems that need parameterizable
two dimensional arrays (and parameterizable elements of
records). Such as floating point types. Right now, binary
operators for complex numbers (with a real and imagniary part)
cannot be implemented.
Proposal 1:
Permit the syntax shown in the component above or permit a
type declaration somewhere in the entity/component declaration
area.
Either of these will probably be difficult in the language
both create a new type and a type conversion would be
needed simpily to do each port map (since each type would
be declared in separate areas.
Proposal 2:
Permit types to be defined of the forms:
Form 1: unconstrained array of unconstrained array
type two_dim_arrayofarray is array(natural <>) of std_logic_vector ;
signal A : two_dim_arrayofarray (Depth-1 downto 0)(Width-1 downto 0) ;
signal A2 : two_dim_arrayofarray (Depth-2 downto 0)(Width-2 downto 0) ;
Currently arrays of arrays are really useful as one can manipulate
a row as follows:
signal D : std_logic_vector(Width-1 downto 0) ;
D <= A(1) ;
A further interesting extension would be to be able to grab a column
as follows:
signal G, H : std_logic_vector(Depth-1 downto 0) ;
G <= A(Depth-1 downto 0)(1) ;
H <= A(all)(1) ;
Since one is really accessing a column of elements of std_logic,
a type conversion may be required:
G <= std_logic_vector(A(Depth-1 downto 0)(1)) ;
H <= std_logic_vector(A(all)(1)) ;
Perhaps further capability, but not justified by this example:
A2 <= A(Width-2 downto 0)(Depth-2 downto 0) ;
Form 2: records with unconstrained array
type rec_w_unconstrained_array is record
array1 : std_logic_vector ;
array2 : std_logic_vector ;
end record ;
-- I don't like the syntax, but here is an idea
signal B : rec_w_unconstrained_array (array1(depth-1 downto 0), array2(width-1 downto 0)) ;
How would one deal with a record that contains both constrained
and unconstrained objects?
Form 3: Two dimensional arrays
type two_dim_array is array(natural <>, natural <>) of std_logic ;
signal C : two_dim_array(Depth-1 downto 0, Width-1 downto 0) ;
signal C2 : two_dim_array(Depth-2 downto 0, Width-2 downto 0) ;
Currently this one is not too interesting because one cannot access
an entire row at a time, but if I could do the following this would
be interesting:
signal D, E, F : std_logic_vector(Width-1 downto 0) ;
D <= C(1, Width-1 downto 0) ;
E <= C(1, all) ; -- all = key word to replace the entire index of that object
E <= C(1, *) ; -- an alternate to all
F <= C(1) ; -- by default if a multidim object is referenced and only one
-- index is specified it is the left most index
-- this may be a bad thing for a strong typed language like VHDL
OOPS, the above probably require type conversion/casting?
D <= std_logic_vector(C(1, Width-1 downto 0)) ;
E <= std_logic_vector(C(1, all)) ;
. . .
Even more interesting, a capability we don't have now:
signal G : std_logic_vector(Depth-1 downto 0) ;
G <= std_logic_vector(C(all, 2)) ; -- all elements from column 2
Perhaps further capability, but not justified by this example:
C2 <= C(Width-2 downto 0, Depth-2 downto 0) ;
If we were to adopt proposal 2 above or something like it,
would this conflict with any of the OO extensions that
could be integrated into DTA. If yes, it cannot be a
fast track issue. Otherwise, I see it qualifying form
the standpoint that it will enable binary operators for
complex typed numeric operations.
Regards,
Jim
Stephen Bailey wrote:
> Jim and Peter,
>
> Cany you two decide whether MP or DTA will be responsible for this issue?
>
> -Steve Bailey
>
> > -----Original Message-----
> > From: Jim Lewis [mailto:Jim@synthworks.com]
> > Sent: Friday, July 11, 2003 6:20 PM
> > To: vhdl-200x@eda.org
> > Subject: [vhdl-200x] [Fwd: Multi-dimentional arrays in
> > components using
> > generics]
> >
> >
> > Another interesting problem.
> >
> > -------- Original Message --------
> > Subject: Multi-dimentional arrays in components using generics
> > Date: Wed, 9 Jul 2003 11:52:35 +0200
> > From: "Willem Oosthuizen" <willy@asic.co.za>
> > Organization: The South African Internet Exchange
> > Newsgroups: comp.lang.vhdl
> >
> > How do I do multi-dimentional arrays in components using generics
> >
> > I tried the following. This does not work. I need to define the type
> > array(Depth -1 downto 0) of std_logic_vector(Width-1 downto 0) and
> > type array(Depth -2 downto 0) of std_logic_vector(Width-2 downto 0)
> > somewhere. But where?
> >
> > COMPONENT Reduce is
> > generic
> > ( Width : integer;
> > Depth : integer
> > );
> > port
> > ( D_IN : IN array(Depth -1 downto 0) of
> > std_logic_vector(Width-1 downto
> > 0);
> > Q : OUT array(Depth -2 downto 0) of
> > std_logic_vector(Width-2 downto
> > 0);
> > );
> > end COMPONENT;
> >
> >
> >
> >
> >
> > --
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > ~~~~~~~~~
> > Jim Lewis
> > Director of Training mailto:Jim@SynthWorks.com
> > SynthWorks Design Inc. http://www.SynthWorks.com
> > 1-503-590-4787
> >
> > Expert VHDL Training for Hardware Design and Verification
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > ~~~~~~~~~
> >
>
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