[vhdl-200x] Object oriented VHDL

Subject: [vhdl-200x] Object oriented VHDL
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue May 13 2003 - 14:16:01 PDT

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I was wondering if anyone has been looking at a more object-oriented
type system
for VHDL - since the competion for simulating systems seems to be C++
(SystemC)
and SystemVerilog, and they both have that.

Since I'm interested in hardware/software trade-off I'd like to see VHDL
adopt a
C++ like scheme (if any) since that makes easier to move algorithmic
code from
C++ (software) to VHDL (hardware) and vice versa.

The scheme used in SystemVerilog is derived from Java via Vera and was
bolted
on in such a way that it doesn't mesh with modules or structs or
interfaces, and isn't
very friendly to synthesis, so it wouldn't be hard to do better with VHDL.

Kev.

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