Subject: Re: [vhdl-200x], vital issues
From: Paul Graham (email@example.com)
Date: Fri Mar 14 2003 - 12:24:29 PST
> According to a paper at DVCon vital is 4X slower than
> Verilog. I would like to see VHDL have a gate level library
> with timing that runs the same speed as Verilog, and one
> without timing that runs faster (200 X faster just like the
> name of the reflector replies :) )
Is there any reason to think that the speed difference is due to features of
the language? How about the fact the verilog has a larger market share then
vhdl, and so it pays for simulator vendors to concentrate on optimizing
their verilog simulators?
On the other hand, is there any reason to think that a vhdl netlist could be
simulated faster than a verilog netlist? Is there anything about vhdl that
makes it more amenable to optimization than verilog at the gate level?
This archive was generated by hypermail 2b28 : Fri Mar 14 2003 - 12:29:42 PST