Subject: Re: [vhdl-200x], vital issues
From: Steve Casselman (sc@vcc.com)
Date: Thu Mar 13 2003 - 10:15:33 PST
Why isn't EDIF appropriate for this kind of thing?
Steve
----- Original Message -----
From: "Ajayharsh Varikat" <ajay@cadence.com>
To: <vhdl-200x@server.eda.org>
Sent: Wednesday, March 12, 2003 10:35 PM
Subject: RE: [vhdl-200x], vital issues
>
> This is an important point. The behavior of Verilog gates
> under VHDL involves both language partitions, and it is difficult
> to get it right by just standardizing the VHDL side of the
> equation. I believe it is important to have a standard that
> encompasses both languages.
>
> regards,
>
> -ajay
>
>
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>
> From owner-vhdl-200x@eda.org Thu Mar 13 04:59 IST 2003
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> From: "John Shields" <jshields@synopsys.com>
> To: <rob@reawebtech.com>, <vhdl-200x@eda.org>
> Subject: RE: [vhdl-200x], vital issues
> Date: Thu, 13 Mar 2003 00:22:33 +0100
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2003
>
> I think it is defining language interoperability
> that is desirable so that mixed language designs have standard
> semantics. Verilog can and should keep the gate-level modeling
> domain. It is a speed issue and an economic issue to maintain
> duplicate gate level libraries.
>
> The # of licenses issue is a business issue, but the interoperability
> problem has been explored and mostly solved (albeit with proprietary
> solutions). Perhaps one of the vendors can propose a standard
> for interoperability to Accellera? This is not really
> just a 200x or 1364 issue, which is what will make it difficult to
> achieve.
>
> Regards, John
>
> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org]On Behalf
> Of Rob Anderson
> Sent: Friday, March 07, 2003 1:57 AM
> To: vhdl-200x@eda.org
> Subject: Re: [vhdl-200x], vital issues
>
>
> Actually the VHDL netlist is not as much as a problem as the
> VHDL gate models. It would be nice to have precompiled libraries,
> whether they came from Verilog or whatever is not of "vital"
> importance. I'd be glad to see less of vital models, they do
> not show VHDL in a good light.
>
> The netlist itself does not lead to inefficiencies, it contains
> no models, just connectivity. I don't see savings to be gained
> by reading in a Verilog netlist over a VHDL netlist.
>
> There are still of course problems reading netlists, mostly
> environmental, library related since the netlist is multi-use.
> Not clear things are better in Verilog.
>
> The SDF is the same regardless, excepting of course that VHDL
> "out" ports cannot be read so one has to artificially inflate
> the design before the VHDL and Verilog netlist signals can have the
> same names. (this issue is on our list) This would be a real
> headache if you tried to read a Verilog netlist into VHDL.
>
> It is worth noting the trend is away from having setup-hold, skew,
> etc. checked in the models. These things are checked in the STA,
> where there is more information than the SDF has. For simulation,
> there is more interest in fast models. So we could have simpler
> VHDL gate models for simulation, if there was any incentive for
> the simulation people to supply them (did you ever see software
> get smaller?)
>
> --Rob
>
> Jim Lewis wrote:
>
> > Francoise,
> > I see there being two aspects to this.
> >
> > 1) Read Verilog Gate-level Netlists
> > Vital is not enjoying the wide support we wished for.
> > Vital is also slow compared to Verilog gate-level netlists.
> > If Vital died, silicon vendors would only need to support
> > one gate-level library format. EDA vendors would no longer
> > need to support Vital. Hence, this would be good for both.
> >
> > However, the current situation is not good for VHDL designers,
> > because to use a VHDL testbench with a Verilog gate-level
> > netlist will cost me two licenses, one for VHDL and one
> > for Verilog. Note for a Verilog designer it would only
> > cost one license.
> >
> > To benefit both users and vendors, it would be best if
> > Verilog gate-level netlists were included as part of the
> > langauge.
> >
> > 2) Standardized Verilog Interface
> > Standardize how to connect a Verilog design to VHDL.
> > This would take us away from a Vendor specific
> > implementation (which at the current time may or may not
> > be identical, but it would be nice if it were documented
> > somewhere in the standard).
> >
> > This of course should and will likely cost two licenses.
> >
> > Cheers,
> > Jim
> >
> > Francoise Martinolle wrote:
> >
> >> I noticed in the priority spreadsheet that a few people (Jim Lewis,
> >> Williams and Bishop)
> >> have voted for read and simulate Verilog netlists.
> >> I was wondering of one of them could provide a short description of
> >> this request.
> >>
> >> thanks
> >> Francoise
> >> '
> >>
> >>
> >
> >
>
>
>
>
> ----- End Included Message -----
>
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