Subject: RE: [vhdl-200x], vital issues
From: Ajayharsh Varikat (ajay@cadence.com)
Date: Wed Mar 12 2003 - 22:35:26 PST
This is an important point. The behavior of Verilog gates
under VHDL involves both language partitions, and it is difficult
to get it right by just standardizing the VHDL side of the
equation. I believe it is important to have a standard that
encompasses both languages.
regards,
-ajay
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