Re: [vhdl-200x] CFA: Priorities


Subject: Re: [vhdl-200x] CFA: Priorities
From: Rob Anderson (rob@reawebtech.com)
Date: Tue Mar 11 2003 - 09:22:48 PST


I agree with proceeding on the plan to add Sugar.

We seem to have a question about how much work it will be, however
we have a commitment from Erich to do much of the work.

I think the first steps should be to set up a reflector, and a
web space to put information, docs, pointers for sugar as it is
being considered for VHDL. I trust Erich that this specification
is useable, but it is necessary to promote what we are doing.

--Rob

Erich Marschner wrote:

> Evan,
>
> | This is an important distinction because No.27 - adding Sugar to the
> | language - is going to be such a vast amount of work that having only 3
> | votes could kill it. However, is it actually the case that it
> | effectively got 10 votes, which would put it pretty much at the top of
> | the priority list? Would anyone else who voted for 'assertions'
> | (Moretti, Lewis, Bailey, Hsu, Martinolle, Anderson) like to comment?
>
> Although I haven't voted (yet), I'd like to comment on this.
>
> "Adding Sugar" to the language may take some work. However, creating a different temporal assertion capability would require enormously more work than would be involved in just integrating the existing PSL/Sugar language constructs into VHDL. Furthermore, the integration task should not be that difficult, if there is consensus to do so. There is a simple and obvious subset of PSL/Sugar that would fit into VHDL nicely as a new kind of concurrent statement that complements and extends the existing concurrent assertion statement. So, if we decide to "add Sugar" to VHDL, it should be possible to do so fairly quickly, with relatively little effort.
>
> Incidentally, I think that this should be a high priority for VHDL 200x.
>
> Regards,
>
> Erich
>
> (Co-Chair, Accellera FVTC)
>
> -------------------------------------------
> Erich Marschner, Cadence Design Systems
> Senior Architect, Advanced Verification
> Phone: +1 410 750 6995 Email: erichm@cadence.com
> Vmail: +1 410 872 4369 Email: erichm@comcast.net
>
> | -----Original Message-----
> | From: Evan Lavelle [mailto:eml@riverside-machines.com]
> | Sent: Tuesday, March 11, 2003 4:36 AM
> | To: VHDL-200x
> | Subject: Re: [vhdl-200x] CFA: Priorities
> |
> |
> | Steve - I see that you've got 'Assertions' as No.8 on the
> | list, with 7
> | votes, and 'Apply Accellera assertions' as No.27, with only
> | 3 votes. I
> | personally voted for 'temporal assertions', and this has actually
> | appeared as a vote for general assertions, ie. 8 rather than
> | 27. This is
> | presumably because you wrote on March 1st:
> |
> | > Finally, I want to point out that I categorized all
> | "temporal assertions"
> | > priorities as a priority for the general Assertion
> | category. The reason being
> | > that VHDL already has combinatorial (or monotonic)
> | assertions. If anyone feels
> | > that I have wrongly jumped to this conclusion on their
> | behalf, please let me
> | > know.
> |
> | I think there may be some disagreement on the classification of
> | 'temporal assertions'. I personally use the phrase to mean
> | the ability
> | to define temporal relationships between specific boolean
> | conditions,
> | and the ability to test the truth or otherwise of those
> | relationships.
> | This is what Sugar and temporal-e do, so it seems to me that
> | a vote for
> | 'temporal assertions' is actually a vote to add the functionality of
> | Sugar (ie. 'Apply Accellera assertions'), temporal-e, or something
> | similar to VHDL.
> |
> | This is an important distinction because No.27 - adding Sugar to the
> | language - is going to be such a vast amount of work that
> | having only 3
> | votes could kill it. However, is it actually the case that it
> | effectively got 10 votes, which would put it pretty much at
> | the top of
> | the priority list? Would anyone else who voted for 'assertions'
> | (Moretti, Lewis, Bailey, Hsu, Martinolle, Anderson) like to comment?
> |
> | Evan
> |
> |
>
>



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