Re: [vhdl-200x], vital issues


Subject: Re: [vhdl-200x], vital issues
From: Steve Casselman (sc@vcc.com)
Date: Fri Mar 07 2003 - 13:48:39 PST


If simulation performance is an issue why not define a modeling system just
built for speed? Then you could have the best of both worlds. For example
you could have functional simulation models are just made for speed. This
could cover 90% of what people simulate. You would then have high
performance mode and high accuracy (Vital) mode.

Steve

> Jim,
>
> If the issue comes down to VHDL gate-level performance, maybe we should
> be asking the tool vendors what we could do to help solve that problem.
>
> Rick
>
> Jayaram Bhasker wrote:
> > Peter:
> >
> > Exactly. This would involve describing the correspondence between
Verilog and
> > VHDL ports as part of the standard.
> >
> > The rules that I have seen so far is:
> >
> > 1. Ports match by name
> > 2. Case sensitive (vhdl port names are case-sensitive) - so user should
use the
> > same case in VHDL as it appears in the verilog module
> > 3. Number of ports must match.
> > 4. VHDL port types can only be std_(u)logic, std_(u)logic_vector.
> > 5. Generics - hmmm, i havent tried/used these - but we could come up
with a reasonble definition.
> >
> > - bhasker
> >
> > ------
> > J. Bhasker, eSilicon Corp
> > 1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104
> > jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)
> >
> >
> > -----Original Message-----
> > From: Peter Ashenden [mailto:peter@ashenden.com.au]
> > Sent: Friday, March 07, 2003 11:07 AM
> > To: Jayaram Bhasker; 'Jim Lewis'; vhdl-200x@server.eda.org
> > Subject: RE: [vhdl-200x], vital issues
> >
> >
> > Bhasker,



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