Subject: [vhdl-200x] CFA, Presentation for DATE Meeting and Results of Initial Prioritization Poll
From: Stephen Bailey (Stephen.Bailey@synopsys.com)
Date: Sat Mar 01 2003 - 11:53:04 PST
The Call for Action (CFA) is for each WG member who did not attend the WG
meeting to review the attached materials and provide to me
(stephen@srbailey.com) their inputs as to the WG's top priorities. Please
provide this information by 10 Mar 03. Here's what I requested at the meeting
combined with what I actually received:
I asked that people identify at least their top 5 priorities but no more than
10.
I received anywhere from 4 to 10 priorities from each person. This is perfectly
acceptable. We want a reasonable number, so a ceiling of 10 provides that.
I asked that people enumerate the priorites.
Some did enumerate their priorities. Many did not. For those who did not
enumerate, I simply assigned all as their 1st choice. Therefore, enumeration is
not critical. It would only help for any priorities that are "on the bubble."
Bubble priorities would deserve further WG discussion or delegation to teams to
determine.
I stated that people could vote for a general area (e.g., Assertions) or for a
specific request.
I received priorities that fell under both categories. I also received
priorities for specific requests which were not already documented in the
presentation. Therefore, please review the priorities_rev1.xls spreadsheet as
well as the presentation material. Also, if you don't see your hot issue, you
can list it as a priority. (A vote for a functional area is relevant. It is a
statement that we must make significant progress in that area. The priorities
within that functional area will be delegated to the fucntional team.)
Finally, I want to point out that I categorized all "temporal assertions"
priorities as a priority for the general Assertion category. The reason being
that VHDL already has combinatorial (or monotonic) assertions. If anyone feels
that I have wrongly jumped to this conclusion on their behalf, please let me
know.
You'll notice that the presentation is updated from the WG presentation which
was previously distributed to this forum. This is the presentation that I am
making available to Dennis Brophy and John Willis to present at DATE. They are
welcome to present / distribute the details in the spreadsheet as well. It is
important that they ensure that attendees at that meeting understand that this
is a first cut and that we want their feedback as well.
I will update the priorities shortly after the CFA suspense date of 10 Mar 03.
The updated version will be distributed to this forum and will also be placed on
eda.org/vasg and distributed on comp.lang.vhdl. I would expect that we would
have a good priority list at that time, but the broader distribution will help
ensure we haven't missed anything that is important.
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Stephen Bailey
Staff Corporate Applications Engineer, VHDL Simulation
Synopsys Inc.
sbailey@synopsys.com
303-775-1655 (voice/mobile)
650-584-4893 (corporate voice mail)
Read Verification Avenue:
http://www.synopsys.com/va
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