RE: Instantiating VHDL components in SystemVerilog.

Hi,

Here is my feedback for some of the questions

Q1. What is the syntax for instantiating a VHDL module/entity inside
    SystemVerilog? It should have the same semantics as instantiating a
verilog module and this how most mixed simulators currently supported.

Q2  Should type parameters be disallowed for VHDL instantiations? 
If the type can be mapped and compatible to SV data type, then it should
be allowed. The idea is to improve the interoperability between the two
languages and not to limit it.

Best Regards
Hassan Shehab                   (480) 554-8398
Intel Corporation               hassan.m.shehab@intel.com
Blackberry Pin                  200DB9A3


-----Original Message-----
From: owner-sv-xc@server.eda.org [mailto:owner-sv-xc@server.eda.org] On
Behalf Of Logie Ramachandran
Sent: Tuesday, March 06, 2007 4:32 PM
To: sv-xc@server.eda.org
Subject: Instantiating VHDL components in SystemVerilog.

Hi Team,

We decided to address SV->VHDL instantiation as our first
topic. We also decided to have a set of questions that
we would like answered as part of this topic. 

I have pulled out some of the questions from 
the survey that pertains to this topic. 

    3.1    What kinds of items would you like to be able to 
           instantiate across VHDL, SystemVerilog boundary
    3.3    What kinds of objects would you like to connect in an
           instantiation that crosses SystemVerilog-VHDL boundary
    3.4    What kinds of data types would you like to see supported
           on "parameters/generics" at the SystemVerilog-VHDL
           boundary
    3.4b   Please list any data type mappings (e.g. VHDL std_ulogic
           to Verilog logic) that are particularly important
    3.5    What kinds of data types would you like to see supported
           on "nets/signals" at a language boundary?
    3.5b   Please list any data type mappings (e.g. VHDL std_ulogic
           to Verilog logic) that are particularly important
    3.6    What kinds of data types would you like to see supported
           on "variables" at the SystemVerilog/VHDL language boundary?
    3.6b    Please list any data type mappings (e.g. VHDL std_ulogic
           to Verilog logic) that are particularly important

Additional questions that are focused on SystemVerilog syntax.
   
Q1. What is the syntax for instantiating a VHDL module/entity inside
    SystemVerilog? 

Q2  Should type parameters be disallowed for VHDL instantiations?
    
Q3. What are the different types of parameters that will be allowed on
the
    instantiation statement.  

Q4. In a multilanguage environment do we need to define
    special attributes in the instantiation  that
    indicates if a module is coming from (a) different language, 
    (b) which one? 

Q5.  Will extern module declarations be extended for VHDL modules?

Q6.  SystemVerilog allows instantiation using 
     i. positional port connections
    ii. named port connections
   iii. implicit .name port connections
    iv. implicit *.port connections

Q7. How will the SV port connection rules be modified for instantiating
    a VHDL component. 
  
Q8. What kind of expressions will be allowed (if any) on the port 
    connections. (eg. partselects, concats). 

Please add other questions that pertain
to instantiating VHDL in SystemVerilog 

Thanks

Logie. 

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