FW: Questions about binding

Forwarding John's email
 
Thanks
 
Logie. 

________________________________

From: John Shields [mailto:John_Shields@mentor.com] 
Sent: Wednesday, March 07, 2007 7:34 AM
To: Logie Ramachandran
Cc: sv-xc@eda.org
Subject: Questions about binding


Hi,

With respect to instantiation and binding among SV, VHDL, and SC, some
assumptions will help to frame the questions and separate issues that
are otherwise closely related.  First, I assume that a design unit from
one language that satisfies an instantiation in another is compatible.
For that to be true, the ports and parameterization of that design unit
must be compatible in kind and type.  By kind, I mean whether it is a
signal, variable, constant, type, etc. and by type I am refering to the
data type,e.g., integer, real, string, wire, std_logic, etc.  A further
characterization of type compatible is 2 types may be compatible if they
are structurally equivalent, or by virtue of strong typing rules
(refering to same single type in each language, for example), or perhaps
by implicit conversion rules.  If an explicit type conversion is
required, then without such conversion, the types are not compatible.

The above assumptions are not meant to define what is compatible with
respect to types, kinds, and design units.  It is just a definitions of
terms and a separate of the issue of compatibility details from
instantiation and binding.

Some initial questions to define the binding and instantiation problem:

1) What is the basic boundary between languages, i.e., are design units
expected to be written entirely in the same language or can foreign
language constructs be used directly within a design unit?

2) Are there any restrictions  on the final structure of a mixed
language elaborated design? May any instance be a design unit from any
other language?

3) In all languages, design units are compiled into libraries and
subsequently, a design may be elaborated from these design units.  Are
there any restrictions on the composition of a library with respect to
the kinds/language of design units it may contain?

4) What order of compilation rules apply in a mixed language context?

5) With respect to each language, what are the design units of that
language and which may be instantiated in which other language?
For example, A VHDL primary design unit may be a package header, an
entity, or a configuration.  Package bodies and architectures are
secondary design units in VHDL.  A VHDL instance is either a package
instance( header plus body, if any) or a component instantiation (
entity/architecture pair).

6) With respect to each language, what are the forms of instantiation of
a design unit in that language and which forms are suitable for
instantiation of foreign design unit?
For example, in VHDL, a package use clause implies package instantiation
and components may be instantiated by direct e/a instantiation, a
component instantiation, or a configuration instantiation.  A component
instantiation may be configured by a component specification, a default
binding rule, or an external configuration.

7) Each language supports parameterization of design units and
mechanisms to bind those parameters to static values at elaboration.
What are the forms of declaring the parameterization of a design unit in
each language?  What are the mechanisms by which such parameters may be
bound in each language?  What binding mechanisms with what restrictions
can be applied to an instance bound to a foreign design unit?
Note, there is an assumption of compatible parameters in kind and type
already that will defined separately.

8) ...questions about finer grained cross-language access within design
units, hier refs, function,procedure, class methods calls need to be
considered...

Regards, John
  




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