SystemC interfacing to SystemVerilog survey questions

(1) At what level should a SystemC model communicate with a
SystemVerilog model ? (choose one or more, use numbers to prioritize,
1 = most important, 2 = less important than 1, X = not required)

    (a) Algorithmic or behavioral
    (b) Communicating processes
    (c) RTL
    (d) Cycle-accurate
    (e) Other, please specify

(2) Use numbers to prioritize the following based on their value
    in interfacing SystemC and SystemVerilog:
   (1 = most important, 2 = less important than 1, X = not required)
    
    (a) Pin-level(rtl) connection between SystemC and SystemVerilog
        using simple built-in types provided by each language.
    (b) Connection between SystemC and SystemVerilog using complex
        types like arrays and structs of built-in types.
    (c) Connecting objects that operate at higher level of abstraction 
        as provided by each language like events, mailboxes, semaphore 
        and fifos.
    (d) Hierarchically referencing external objects defined in one
        language from another.
    (e) Pass parameters across the language boundary.
    (f) Other, please specify

 
(3) Additional comments ?

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