SV-XC: VHDL Interoperability Survey Questions

1. What kinds of Verilog/SystemVerilog items would you like
   to be able to instantiate from VHDL and vice versa? 
       - Modules/Architectures
       - SV Interfaces
       - SV Program Blocks

2. Would you like to have an integrated mechanism for 
   configuring instantiations at a language boudnary? 

3. What kinds of objects would you like to connect in an
   instantiation that crosses a language boundary?
       - Parameters/generics
       - Ports that are nets/signals
       - Ports that variables
       - Shared/reference variables
       - Other. Please explain.

4. Data type support for constant objects

  a. What kinds of data types would you like to see supported
     on parameters/generics at a language boundary?
       - Bit
       - 4-state logic 
       - Real
       - Time
       - Dynamic data types. If so, which ones?
       - Enumerations
       - Arrays of bit/logic
       - Arrays of other data types. If so, what data types?
       - Structs/Records. If so, packed, unpacked, or both?
       - Other. Please explain.

  b. Please list any data type mappings (e.g. VHDL std_ulogic
     to Verilog logic) that are particularly important

5. Data type support for signals

   a. What kinds of data types would you like to see supported
      on nets/signals at a language boundary?
       - Bit
       - 4-state logic with strength
       - Real
       - Time
       - Enumerations
       - Arrays of logic
       - Structs/Records 

  b. Please list any data type mappings (e.g. VHDL std_ulogic
     to Verilog logic) that are particularly important

6. Data type support for signals

   a. What kinds of data types would you like to see supported
      on variables at a language boundary?
       - Bit
       - 4-state logic 
       - Enumerations
       - Arrays of bit/logic
       - Arrays of other data types. If so, what data types?
       - Structs/Records. If so, packed, unpacked, or both?
       - Real
       - Time
       - Dynamic data types. If so, which ones?
       - Other. Please explain.

  b. Please list any data type mappings (e.g. VHDL std_ulogic
     to Verilog logic) that are particularly important

7. What network semantics would you like to preserved across
   a language boundary?
       - 2-state
       - Multiple drivers
       - trireg
       - bidirectional transistor networks
       - Verilog strength
       - Other. Please explain.

8. What kinds of behavioral code would you like to be able to call
   across a language boundary?
       - Functions
       - Tasks
       - Procedures 

9. What kind of integrated interprocess synchronization would you like 
   to see in a mixed-language simulation (events, semaphores, etc.)?
   Please explain.

10. Would you like an integrated I/0 mechanism?

11. Would you like to have integrated access to timing backannotation
   (Verilog SDF and VHDL VITAL)? Clocking blocks?

12. Would you like to see VPI extended to reach across languages
   to other APIs (e.g. VHPI)?

13. Would you like to be able to directly reference objects
    that are declared in a different language (through a hierarchical
    reference)? If so, what kinds of objects, and from what contexts?

14.

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