Re: SystemC interfacing to SystemVerilog survey questions

> From:     Saha, Arnab <arnab_saha@mentor.com>
>
> (1) At what level should a SystemC model communicate with a
> SystemVerilog model ? (choose one or more, use numbers to prioritize,
> 1 = most important, 2 = less important than 1, X = not required)
>
>    (a) Algorithmic or behavioral
>    (b) Communicating processes
>    (c) RTL
>    (d) Cycle-accurate
>    (e) Other, please specify

I'm not sure what you mean by your categories.

I would assume that it would be fairly easy to hand off all the 
scheduling for SystemC to the SV/VHDL/AMS simulator if there was an API 
for that. Most of the rest of the communication will be through 
signals/events (which just happens when it happens).

>
> (2) Use numbers to prioritize the following based on their value
>    in interfacing SystemC and SystemVerilog:
>   (1 = most important, 2 = less important than 1, X = not required)
>       (a) Pin-level(rtl) connection between SystemC and SystemVerilog
>        using simple built-in types provided by each language.
1
>    (b) Connection between SystemC and SystemVerilog using complex
>        types like arrays and structs of built-in types.
2
>    (c) Connecting objects that operate at higher level of abstraction 
>        as provided by each language like events, mailboxes, semaphore 
>        and fifos.
2

1 for mailboxes/fifos, since they are a good mechanism for communicating 
between different kinds of processes.
>    (d) Hierarchically referencing external objects defined in one
>        language from another.
2 +/-
     - suspect SystemC is more likely to be on top so it's unlikely 
[System]Verilog would want to reference it.
>    (e) Pass parameters across the language boundary.
1.5
>    (f) Other, please specify

>
> (3) Additional comments ?
>
Assuming single thread of control?

Kev.

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