Re: [P1800] P1800 SystemVerilog Ballot Draft (4.0) is ready

From: <Shalom.Bresticker_ f rom _freescale.com>
Date: Wed Feb 16 2005 - 11:36:50 PST
Also, I'd like to take this opportunity to inform you that I intend to 
end my editorship of the 1364 LRM in the near future, due to severe 
limitations on my time affecting my ability to fulfill my obligations to
my employer.

I had already stated anyway that I would be unable to perform the 
changes to the document for the recirculation ballot, due to the Passover
holiday.

-- 
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Verification Methodology                    Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                 Fax: +972 9  9522890
POB 2208, Herzlia 46120, ISRAEL                     Cell: +972 50 5441478
  
[ ]Freescale Internal Use Only      [ ]Freescale Confidential Proprietary
Received on Wed Feb 16 11:36:55 2005

This archive was generated by hypermail 2.1.8 : Wed Feb 16 2005 - 11:36:56 PST