[P1800] THANKS!

Hi Shalom,

I would like to use this opportunity to thank you personally and on behalf 
of the P1800 WG as well as P1364 sub-WG for your outstanding and valuable 
contributions to Verilog 1364 LRM and SystemVerilog. Your passion and 
round-the-clock work have been impressive!

Thanks!

--- Johny.






Shalom.Bresticker@freescale.com 
Sent by: owner-ieee1800@eda.org
02/16/2005 01:36 PM
Please respond to
Shalom.Bresticker


To
Johny Srouji/Austin/IBM@IBMUS
cc
ieee1800@eda.org
Subject
Re: [P1800] P1800 SystemVerilog Ballot Draft (4.0) is ready






Also, I'd like to take this opportunity to inform you that I intend to 
end my editorship of the 1364 LRM in the near future, due to severe 
limitations on my time affecting my ability to fulfill my obligations to
my employer.

I had already stated anyway that I would be unable to perform the 
changes to the document for the recirculation ballot, due to the Passover
holiday.

-- 
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Verification Methodology                    Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                 Fax: +972 9  9522890
POB 2208, Herzlia 46120, ISRAEL                     Cell: +972 50 5441478
 
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