Date: Thu Feb 10 2011 - 06:01:14 PST
When we discussed deferred association of resolution yesterday, I had forgotten the conclusion we had reached on the reflector. The conclusion of the thread was that parasitics can be modeled without customized resolutions functions; or at least gross approximations of parasitics can be modeled. In order to do so, however, each Thevenin driver must be parameterized to include an additional parasitic resistance that will be updated by the back annotation tool. It's not a process that's completely invisible to the modeler, but it is functional.
Ultimately, for a sophisticated model of parasitic interconnect with complicated legs and branches, a module with state will be required. This could be instantiated in a flattened layout driven netlister, as shown below. What the disadvantages of such an approach are not clear to me. For some reason, it appears that a lot of emphasis is placed on keeping a single netlist for all applications, and back annotation ad timing information simply layers on top of the unmodified netlist. The motivation for this is not clear and the proposed flattened netlist may conflict with that philosophy.
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For example,
Kindest Regards,
Jim Lear
Cirrus Logic
(512) 851-4612
(512) 293-7248 (mobile)
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