[sv-dc] Back Annotation

Here's the old AMS back-annotation proposal:

http://www.eda-twiki.org/verilog-ams/htmlpages/tc-docs/issues/misc/back_ann.pdf
http://www.eda-twiki.org/cgi-bin/view.cgi/VerilogAMS/BackAnnotationProposal

- put simply:

Add syntax for breaking a port connection and reconnecting the top and
bottom sides to other places in the design.

In the absence of alternatives, I think it would be good to consider it
as something to be supported by whatever scheme for user-defined defined
types and resolution SV-DC adopts.

Kev

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