[sv-dc] Disciplines from AMS

From the last AMS meeting it seems like there is a fairly strong
commitment to bringing the Verilog-AMS stuff into SV sooner rather than
later.

The disciplines section of Verilog-AMS is fairly independent, and is a
useful framework for adding attributes to nets. Does anybody have an
objection to assuming that it is available for the SV-DC work?

Disciplines are the correct place to put attributes about Vdd/Vss, logic
thresholds and other technology dependent info. It's useful for adding
rules about what things can/cannot be connected, e.g. generic types like
wreal can also be marked as having a discipline, and nets can only have
one base discipline, so you can avoid accidentally connecting an
electrical wire to a fiber-optic, or a 1V logic to a 2V logic (by
connect rules).

Kev.

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