[sv-dc] on late resolution function association - conversion state & back annotation

Verilog-AMS connect module insertion is essentially a late-associating resolution scheme. The fact that modules are used rather than functions is because the conversions need to maintain state. It seems likely that will be required for SV discrete modeling too (regardless of supporting actual analog).

Ideally, the process for determining the elaboration/resolution methodology is

   1. elaborate
   2. back-annotate
   3. determine drivers (& receivers) on nets
   4. pick resolution schemes
   5. add connect modules where necessary
   6. re-evaluate from 3

Step (6) is required because connect modules may add more drivers and receivers.

Any scheme that cannot support back-annotation should be rejected in my opinion because a lot of the motivation for tackling this problem is the dominance of wiring effects (post P&R), where SDF is insufficient.

Kev.

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