RE: [sv-dc] Disciplines from AMS

Hi Kevin:

Yes, I object. The work currently being discussed in SV-DC must be finished by Oct. 1, 2011. The merger between SV and VAMS will not be completed in that time, so we should not assume anything from that merger will be available to us. It is not within the scope of SV-DC to do any merger work, so we should not consider adding disciplines to SV as part of our work.

Thanks,
Scott

> -----Original Message-----
> From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of
> Kevin Cameron
> Sent: Monday, February 07, 2011 12:57 PM
> To: sv-dc@eda.org
> Subject: [sv-dc] Disciplines from AMS
>
>
> From the last AMS meeting it seems like there is a fairly strong
> commitment to bringing the Verilog-AMS stuff into SV sooner rather than
> later.
>
> The disciplines section of Verilog-AMS is fairly independent, and is a
> useful framework for adding attributes to nets. Does anybody have an
> objection to assuming that it is available for the SV-DC work?
>
> Disciplines are the correct place to put attributes about Vdd/Vss,
> logic
> thresholds and other technology dependent info. It's useful for adding
> rules about what things can/cannot be connected, e.g. generic types
> like
> wreal can also be marked as having a discipline, and nets can only have
> one base discipline, so you can avoid accidentally connecting an
> electrical wire to a fiber-optic, or a 1V logic to a 2V logic (by
> connect rules).
>
> Kev.
>
>
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