RE: [sv-dc] 4-state vs 3-D

Scott,

Even in 'classic Verilog', X is used sometimes to mean that the net may be in neither a 0 nor a 1 state.
The X is an abstraction that allows you to deal with that case in logic-level modeling.
Examples of how that can occur are undriven nets, or nets that are driven simultaneously by sources with different values.

Regards,
Shalom

> What does 'X' mean in logic modeling: the net is in a 1 or 0 state, but
> I don't know which. Note that X does *not* necessarily mean "it is
> floating somewhere between the two voltage levels corresponding to the
> logic values" since the notion of voltage levels is an implementation
> (hardware implementation) detail. In pure logic modeling there is 0 or
> 1, that's it.
>
> Now X's arise from two sources (in classic Verilog):
> 1) uninitalized behavioral constructs such as registers
> 2) nets driven with strength-modeled drivers which result in an
> ambiguous strength or undriven strength (Z).

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