RE: [sv-dc] 4-state vs 3-D

In pure logic modeling, you are always in 0 or 1. For instance, an and gate can only output a 1 or 0. And in real hardware, an and gate will always output Vhi or Vlo, even if the input is sitting at some midpoint voltage (in which case you don't know which one however). Another way of saying this is that the gate will always consider the floating input as 0 or 1, but you cannot predict which one. Even with an X input, a logic operation will always put out an output value which can come about from the input being 0 or 1 - it won't put out some silly meaningless value.

I know this sounds like splitting hairs but I feel it its terribly important to figure out what real modeling is supposed to represent before we can define it. The concept of X is part of this.

 -- Scott

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
Sent: Thursday, December 09, 2010 10:31 AM
To: Scott Cranston; Kevin Cameron; Arturo Salz
Cc: sv-dc@eda.org
Subject: RE: [sv-dc] 4-state vs 3-D

Scott,

Even in 'classic Verilog', X is used sometimes to mean that the net may be in neither a 0 nor a 1 state.
The X is an abstraction that allows you to deal with that case in logic-level modeling.
Examples of how that can occur are undriven nets, or nets that are driven simultaneously by sources with different values.

Regards,
Shalom

> What does 'X' mean in logic modeling: the net is in a 1 or 0 state, but
> I don't know which. Note that X does *not* necessarily mean "it is
> floating somewhere between the two voltage levels corresponding to the
> logic values" since the notion of voltage levels is an implementation
> (hardware implementation) detail. In pure logic modeling there is 0 or
> 1, that's it.
>
> Now X's arise from two sources (in classic Verilog):
> 1) uninitalized behavioral constructs such as registers
> 2) nets driven with strength-modeled drivers which result in an
> ambiguous strength or undriven strength (Z).

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