RE: [sv-dc] 4-state vs 3-D

Hi Scott,

Interesting notion and a valid discussion. As far as I can tell the added value of X in a real valued net can be:
- I don't know (Undefined)
- I cannot determine (Undetermined)
- I don't care (Irrelevant)

The first is a situation that might come out of an initialization: at the start of initialization some logic states may be undefined and the state of some real data may also be undefined. At the end of initialization all states should be defined. Using a real 'X' would allow one component to tell another over a (real) wire that it has not yet been initialized - something that could point to a potential start-up issue.

The second situation occurs when two real values of equal strength and opposite values are driving the same net, as Shalom has already pointed out.

The third situation would again arise during initialization but then for real signals that should not have an impact. Consider for instance an analog block that has been in power-down mode and that is starting up. At a higher abstraction level the actual value at start-up might be largely irrelevant so the model would output an 'X' until the voltage is stable and the environment of the analog block can be allowed to pick up signals/supplies from it. The use of 'X' would enforce the blocks to wait for a proper signal - 'Z' would not be a correct state in this case as in power-down of the analog block 'Z' could be the proper signal.

For me, the added value of 'Z' and 'X' are at higher abstraction levels for the analog or mixed-signal part of the design.

Cheers,
Marq

Marq Kole
Product Manager AMSRF Simulation
NXP Semiconductors / Central R&D / Foundation Technology

-----Original Message-----
From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of Scott Cranston
Sent: Thursday 9 December 2010 16:22
To: Kevin Cameron; Arturo Salz
Cc: sv-dc@eda.org
Subject: RE: [sv-dc] 4-state vs 3-D

First question to answer:

What does the notion of 'X' mean in the real valued space? Which is another way of saying "what does real modeling" mean? All else is just semantics.

What does 'X' mean in logic modeling: the net is in a 1 or 0 state, but I don't know which. Note that X does *not* necessarily mean "it is floating somewhere between the two voltage levels corresponding to the logic values" since the notion of voltage levels is an implementation (hardware implementation) detail. In pure logic modeling there is 0 or 1, that's it.

Now X's arise from two sources (in classic Verilog):
1) uninitalized behavioral constructs such as registers
2) nets driven with strength-modeled drivers which result in an ambiguous strength or undriven strength (Z).

Let's ignore the first for purposes of this discussion. In the second, the X's arise from a lower level of modeling abstraction (strength or switch-level modeling) which understands "more" about the world then just 0 or 1. For purposes of logic modeling, Z can be treated the same as X when considered as an input, however it should be noted that pure logic operations *never* result in an X - you need that lower level of abstraction to generate them.

We need to do a similar analysis of real level modeling: what does an 'X' mean, i.e. what type of modeling requires the notion of an X *in the real domain itself* ? Is real modeling a lower level of modeling than logic, so that it can introduce X's into the logic world, or is it a higher level of modeling, which merely encapsulates the logic values in some other form. In other words, does it know more about the world, or less?

 -- Scott

-----Original Message-----
From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of Kevin Cameron
Sent: Wednesday, December 08, 2010 7:26 PM
To: Arturo Salz
Cc: sv-dc@eda.org
Subject: Re: [sv-dc] 4-state vs 3-D

To look at it slightly differently: if the user wants to encode their X/Z net states as NaN, how will they do that?

You could do the X/Z stuff by having the real-value resolution function return a composite type that includes bits to indicate that the value is uncertain or the net is undriven, and have the receiver conversion do the translation to NaN - the local type being a simple real value, the net/resolved type being the one you use for the X/Z tests.

And/or you could let users annotate types with which values in the type represent X or Z, e.g. something like:

  typedef real real3d (z => NaN,x => NaN); // gives NaN as initial and undriven value

Users probably need to be able to test for NaN and set things to be NaN anyway, so I'd say just push it into user space.

Kev.

On 12/08/2010 01:20 PM, Arturo Salz wrote:
> I think discussing a particular encoding is not a good solution. If the capability to represent X and Z for real numbers is built into the language then the particular encoding becomes an implementation detail. Note that for the digital domain, the encoding of X/Z used by the simulation kernel is not visible to users (even when some API's make it seem so).
>
> What you seem not be discussing here is an encoding that can be adopted by convention, and, as long as the same value can be deposited on the floating-point variable by some other mean then there is ambiguity as to whether that particular value is indeed a Z, an X, or some other malformed number due to some other reason. This does bring up some real use issues, for example, how should a waveform tool display a floating-point variable that contains NaN: should it show NaN, Z, X.
>
> I contend that the X / Z should be handled internally by the implementation. Attempting to formalize the encoding using an existing floating-point value seems like a memory optimization to avoid storing the information elsewhere (say 2 more bits), which is probably not the best use of the committee. This something that the implementation can better address.
>
> Arturo
>
> -----Original Message-----
> From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of Achim Bauer
> Sent: Wednesday, December 08, 2010 12:42 PM
> To: Kevin Cameron
> Cc: sv-dc@eda.org
> Subject: Re: [sv-dc] 4-state vs 3-D
>
> Hi Kev,
>
> looks good, just my analog five cents:
>
> In the analog or real domain "x" or undefined might be interpreted as
> undriven (strength=0!) or floating. A floating or high-impedance
> (strength=0) node can not really maintain a stable signal, it is prone
> to any kind of (unknown) disturbances, the (voltage) value is kind of
> undefined. For real values z and x are kind of the same.
>
> So one might even code it in a 2-dimensional way:
>
> Value ( real: -inf -> +inf )
> Strength ( real: undriven/undefined = 0, driven = ]0:+inf) )
>
> Which would comply nicely with a sparse struct notation.
>
> Achim
>
>
> On Wed, 2010-12-08 at 09:13 -0800, Kevin Cameron wrote:
>> 4-state refers to the received values "0,1,Z,X", since 0,1 are the range of known good logic values (for a single bit), the same nomenclature doesn't really apply for real values (since there are a lot of valid discrete values).
>>
>> I'd prefer to call it "3-Dimensional", the dimensions being:
>>
>> Value (logic: 1,0, real: -inf -> +inf)
>> Strength (undriven = z, regardless of type)
>> Certainty (uncertain logic = x, uncertain real = NaN)
>>
>>
>> Comments?
>>
>> Kev.
>>
>>
>

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