RE: [sv-dc] Freescale SV-DC Roadmap Content

Hi Kevin:

I mean that different types of drivers will be used in the same
simulation/configuration run. I have attached a pdf with 3 figures that
I hope clarify some bits of the Freescale roadmap contribution. The
first two figures correspond to the two use cases. The final figure
refers to the final requirement.

Thanks,
Scott

> -----Original Message-----
> From: Kevin Cameron [mailto:edaorg@v-ms.com]
> Sent: Friday, August 13, 2010 6:40 PM
> To: Little Scott-B11206
> Cc: sv-dc@eda.org >> "sv-dc@eda.org"
> Subject: Re: [sv-dc] Freescale SV-DC Roadmap Content
>
> On 08/13/2010 01:33 PM, Little Scott-B11206 wrote:
> > ...
> >
> > Freescale SV-DC Roadmap Content
> > ...
> >
> > 1. Motivation and Use Cases [why]
> >
> > -There are several cases in our designs where we have mixed I/Os.
> The same wire may be driven at times by a digital clock and at other
> times by an analog voltage. Modeling these I/Os as real/composite
nets
> gives us an acceptable accuracy/performance trade-off.
> >
> >
>
> - just for clarification: do you mean different types of drivers in
the
> same simulation configuration/run, or that different
> configurations/runs
> will have either digital or analog for the I/O on some block?
>
> A goal I think might be worth adding is VHDL compatibility, i.e. types
> and mechanisms used in VHDL can be duplicated in SV so that SV is a
> superset of VHDL.
>
> Kev.
>

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