Re: [sv-dc] Freescale SV-DC Roadmap Content

On 08/13/2010 01:33 PM, Little Scott-B11206 wrote:
> ...
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> Freescale SV-DC Roadmap Content
> ...
>
> 1. Motivation and Use Cases [why]
>
> -There are several cases in our designs where we have mixed I/Os. The same wire may be driven at times by a digital clock and at other times by an analog voltage. Modeling these I/Os as real/composite nets gives us an acceptable accuracy/performance trade-off.
>
>

- just for clarification: do you mean different types of drivers in the
same simulation configuration/run, or that different configurations/runs
will have either digital or analog for the I/O on some block?

A goal I think might be worth adding is VHDL compatibility, i.e. types
and mechanisms used in VHDL can be duplicated in SV so that SV is a
superset of VHDL.

Kev.
 

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