Re: [sv-dc] Freescale SV-DC Roadmap Content

There was an entire committee in the 1800-2005 PAR for
dealing with "interoperability" with the first target
being SV/VHDL (SV-XC). Died a pretty ugly death for
lots of reasons.

I would suggest staying away from any direct VHDL
compatibility statements/requirements. Obviously
in practice, the vendors will care about it, but
trying to standardize anything involving that is likely
not going to be a winning strategy in terms of doing
things for this PAR.

Defining requirements that are a superset of VHDL is
fine as a direction, but you don't want to talk about
that in terms of "compatibility" or probably in any
way talk about requirements that lead people to
considering what happened with SV-XC and writing off
the entire effort.

Gord.

Kevin Cameron wrote:
> On 08/13/2010 01:33 PM, Little Scott-B11206 wrote:
>> ...
>>
>> Freescale SV-DC Roadmap Content
>> ...
>>
>> 1. Motivation and Use Cases [why]
>>
>> -There are several cases in our designs where we have mixed I/Os. The same wire may be driven at times by a digital clock and at other times by an analog voltage. Modeling these I/Os as real/composite nets gives us an acceptable accuracy/performance trade-off.
>>
>>
>
> - just for clarification: do you mean different types of drivers in the
> same simulation configuration/run, or that different configurations/runs
> will have either digital or analog for the I/O on some block?
>
> A goal I think might be worth adding is VHDL compatibility, i.e. types
> and mechanisms used in VHDL can be duplicated in SV so that SV is a
> superset of VHDL.
>
> Kev.
>
>

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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