[sv-dc] Re: Framework directions for discrete modeling

[apologies for resend on previous reply - server problems]

I'm happy to propose stuff, but I think it would be better to get an
idea of what people are trying to achieve first. Are we looking to
support power management verification/modeling, PLL behavioral models,
RF or something else?

Presumably if we are not doing a full AMS now, we'll still want to do it
later, so things should be designed to be forward compatible.

Kev.

On 07/27/2010 11:36 AM, Gordon Vreugdenhil wrote:
>
>
> Kevin Cameron wrote:
> [...]
>
>> The user community wants user defined types on wires, SV has classes for
>> defining types. You can use the class inheritance mechanism to take base
>> classes and add different resolution schemes, which makes it easier to
>> work out which types are compatible. It's fairly easy to make the
>> parsers recognize net assignments and do driver creation/insertion
>> rather than doing the manual driver stuff in Ken's proposal.
>>
>> It's pretty similar to what's in VHDL for user defined types, so I'm not
>> seeing this as a hard problem.
>
>
> Please feel free to make a proposal.
>
> I have no vested interest in any particular direction. If
> you believe that an object based approach is feasible (including
> all the object creation and topology semantics), please suggest
> what you think needs to changed in SV to have things work.
>
> Gord

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