Kevin Cameron wrote:
> Resolution in Verilog is flat, i.e. hierarchy is not considered. VHDL
> does not not do flat resolution, and that can give incorrect behavior
> for AMS.
I don't see were this could be a problem for a properly formed
resolution function. Thevenin and Norton resolution functions are
fairly robust.
Kindest Regards,
Jim Lear
Cirrus Logic
(512) 851-4612
(512) 293-7248 (mobile)
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