Kevin Cameron wrote:
[...]
> The user community wants user defined types on wires, SV has classes for
> defining types. You can use the class inheritance mechanism to take base
> classes and add different resolution schemes, which makes it easier to
> work out which types are compatible. It's fairly easy to make the
> parsers recognize net assignments and do driver creation/insertion
> rather than doing the manual driver stuff in Ken's proposal.
>
> It's pretty similar to what's in VHDL for user defined types, so I'm not
> seeing this as a hard problem.
Please feel free to make a proposal.
I have no vested interest in any particular direction. If
you believe that an object based approach is feasible (including
all the object creation and topology semantics), please suggest
what you think needs to changed in SV to have things work.
Gord
-- -------------------------------------------------------------------- Gordon Vreugdenhil 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jul 27 11:37:18 2010
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