[Actual] Notes for meeting on 2010-05-25

Please let me know if there are any corrections.

Thanks,
Scott

2010-05-25
SV-DC meeting notes

Attendees:
11 Jim Lear (Cirrus)
11 Achim Bauer (obs)
11 John Havlicek (Freescale)
11 Scott Little (Freescale)
11 Scott Cranston (Cadence)
11 Sundaram Sangameswaran (TI)
11 Gord Vreugdenhil (Mentor)
11 Top Lertpanyavit (Intel)
11 Dana Fisman (Synopsys)
11 Ghassan Khoory (Synopsys)
11 Ian Wilson (BDA)
1- Ken Bakalar (Mentor)
1- Kevin Cameron (obs)
1- Arturo Salz (Synopsys)
1- Dave Cronauer (Synopsys)
1- Ed Cerny (Synopsys)
1- Tapan Halder (Synopsys)
1- Jonathan David (obs)
1- Jim Holmes (Lynguent)
SUMMARY:

-SV-DC scope was approved and will be presented to the P1800 WG. The
final version can be found at: http://bit.ly/cWIN31

-The meeting time was decided to be 9:00 a.m. Central time for two
hours. We will meet every other week. The next meeting will be on
2010-06-08.

-As we move to discussion of the roadmap it will be useful for people to
share written ideas about the features and capabilities they would like
to see and where they might fit in the short and long term phases of
development. Examples and descriptions of use cases tend to be very
helpful.

DETAILS:

GV moved that the patent policy be considered read. SL seconded. 0
against and 0 abstain.

JH: The main purpose today is to decide on a scope. That has been out
there in a Google document. I saw some e-mail from Gord and Achim about
some wording changes. I have made the first change. There was some
discussion about the second statement. What do we want to do there?

GV: I want to be careful in thinking about the target audience which is
the SV community. They are digital centric and we want to be careful
about using the term AMS. I am comfortable with this, but I think the
general reader might be confused about whether we want or don't want
mixed-signal features included.

AB: I would like to change the second sentence there because it seems to
say that Verilog-AMS models can't be discrete which isn't true. Why
don't we say continuous or conservative.

IW: I would be in favor of removing Spice and Verilog-AMS entirely.

SS: This gives me the feeling of a bottom-up flow. They can also be
used in a top-down flow.

JL: Maybe we should say interchanged. We need to get rid of the
directionality here.

GV: You are reading too much into the sentence. It isn't stating a
development flow. It is trying to say that if such a model exists the
language should have features that allow interoperability.

SS: In the last meeting a number of details regarding data types came
out. Somehow this seems like it is missing.

JL: Doesn't the first paragraph address this?

GV: You want to be careful with the scope document to give understanding
as to what is under consideration without giving a work list. The
roadmap will look at the scope and then give more details about what
exactly is going to be done.

JH: What about the date for the roadmap?

AB: What about the roadmap document? 20-30 pages?

JH: I hope not. I was thinking maybe 5 pages. It needs to identify
work items and effort for these items. The goal is to crisply define
what will be worked on and give a plan to accomplish useful work within
the next PAR. It seems useful to also mention some future directions.

GV: My only concern about the timeframe is a personal one. I am going
to be gone from mid-June to early July and will be completely
unavailable. I don't know how many other folks have summer plans? I
think that mid-September is pretty reasonable.

JH: Okay, how about we say mid-September.

GV: If the roadmap is concise enough and precise enough the roadmap may
lead us directly to the necessary proposals which would be great.

AB: What is the interaction with ASVA and Verilog-AMS?

JL: This idea is implied in the statements about plug and play models.

JH: I hope that we have made it clear that we have participation from
Verilog-AMS. My opinion is that we should generalize wreal.

JL: Is that a part of the scope document?

JH: No.

GV: I think that was in the general discussion last week. wreal has
issues due to the fact that it can only express a single real at a time.
That is a limitation.

JL: It seems to me that this scope document represents this point of
view.

GV moves that we approve the current SV-DC scope document as currently
written in Google docs. SL seconds.

JL: One must be a dues paying member to vote?

GV: The rule that we are operating under is that this is study work
under the old PAR. The new PAR has not yet been officially approved.
The rule is that you have to have attended 2 out of the last 3 meetings
or 75% overall. During the first three meetings everyone has the right
to vote.

Motion passed with 0 against and 0 abstain.

SS: When is the next meeting? Is it okay to do 9:30-10:30?

JH: We only want to have 1 hour meetings?

GV: 1 hour tends to not be enough time for technical discussion.

JH: Okay, we will align with the other 1800 committees in the week and
we will be 9-11 am central which is currently UTC-5.

GV: The next meeting is the 8th then?

JH: Yes, but I won't be here. Scott, can you lead the meeting?

SL: Yes.

JH: It would be nice if others could help with administrative
responsibilities. Please think about that.

SS: Roadmap is the topic for the next meeting?

JH: Yes, the homework would be start thinking about what we want to
accomplish in the next PAR as well as potentially moving forward.

AB: If I write down some thoughts is it too detailed to write up 1 or 2
pages right now?

GV: I think that would be valuable. I am personally working on some
descriptions of what I would like to see. That is still subject to
internal review. I think that getting a few perspectives written up
independently is nice. That way we can try to shake out the common
ideas. I would particularly like to see something from an AMS
perspective. I have understanding of the area, but I am not an expert.
Then having someone from a digital perspective write up to see what fits
and look at the common points would be good.

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