Re: [Actual] Notes for meeting on 2010-05-25 - wreal

Just FYI: I have a long-standing issue in Mantis that wreal should be
deprecated -

http://www.verilog.org/mantis/view.php?id=2378

- I'd be extremely happy to see it replaced be some user-defined type
scheme (the Mantis proposal had a narrower scope).

I mention it because there are some other issues to do with disciplines
and access functions. As a user I think you want to be able to use the
same syntax in different contexts to mean the same thing, i.e. in a
Verilog-AMS analog block "V(x) <+ value" assigns a voltage, and I think
it would be good to have the same syntax in a digital block with
whatever the replacement for wreal is (when that's what the user intends).

The "V" function is defined in the "electrical" discipline (in
Verilog-AMS), and maps to the more generic "potential" ("I" maps to
"flow"), so I think it would be a good idea to have potential and flow
methods defined in the (user defined) signal classes.

The discipline typing is mostly just an attribute scheme, it gets used
in AMS for determining which things can be connected and which connect
modules to use. It could be used to stop accidental power/voltage-domain
crossing connections (which should have level shifters) in an
all-digital context.

Kev.

On 05/25/2010 12:48 PM, Little Scott-B11206 wrote:
> ...
>
> JH: I hope that we have made it clear that we have participation from
> Verilog-AMS. My opinion is that we should generalize wreal.
>
> JL: Is that a part of the scope document?
>
> JH: No.
>
> GV: I think that was in the general discussion last week. wreal has
> issues due to the fact that it can only express a single real at a time.
> That is a limitation.
> ..
>

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