SV-DC scope

Hi Folks:

SV-DC today approved a statement of scope, which I have copied below.
This is also in a Google doc that can be accessed from the following
url:

http://bit.ly/cWIN31

J.H.

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SV-DC Scope:

The SV-DC committee will investigate and recommend a roadmap for
discrete modeling features within SystemVerilog. Limiting the scope
to discrete modeling means there is not an intention to bring the
analog solver into SystemVerilog. The near term roadmap will likely
include nets and ports of generic data types, resolution functions,
and type conversion mechanisms. Longer term, the roadmap may include
features for piece-wise linear waveform definition and support for
several modeling styles (e.g., timed data driven, signal flow,
modeling with restricted conservative linear networks). It is
expected that these features can exist in SystemVerilog without
requiring
a merge of the SystemVerilog and Verilog-AMS standards.

The primary use case motivating this work is the need for high speed
simulation of models of analog blocks. Faster discrete models will be
interchangeable in a plug and play style with continuous or conservative
models.

The roadmap will focus on the items to be completed within the 2012 PAR,
but will also provide vision for future directions. It will identify
the
new discrete modeling features and describe how they will interact with
current SystemVerilog features. It may also include recommendations
of how these features interact with VHDL and/or Verilog-AMS. The
initial roadmap will be completed no later than September 15, 2010.

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