[sv-ac] RE: Call to vote. Due August 30

SVDB 2205 _X__Yes ___No
http://www.eda-stds.org/mantis/view.php?id=2205
http://www.eda-stds.org/mantis/file_download.php?file_id=4489&type=bug

SVDB 2571 _X__Yes ___No
http://www.eda-stds.org/mantis/view.php?id=2571
http://www.eda-stds.org/mantis/file_download.php?file_id=4414&type=bug

SVDB 3035 __X_Yes ___No
http://www.eda-stds.org/mantis/view.php?id=3035
http://www.eda-stds.org/mantis/file_download.php?file_id=4485&type=bug

I think that there is no confusion as to what should or should not be sampled. Already now in modules, variables that are use in deferred and immediate assertions are not sampled, those used in concurrent assertions (other than automatics, etc.) are sampled. In checkers it just adds that if used on rhs of assignments design variables are sampled

The question may arise once procedural control statements are used, allowing for automatic variables. should these be sampled or not? But that should be resolved when such statements are added. I think that the proposal on sampling should not depend on it.
(I.e. I disagree with John's solution to control sampling.)

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