Re: [sv-ac] Call to vote. Due August 30 (reminder)

My votes:

>
> SVDB 2205 _x__Yes ___No
>
> http://www.eda-stds.org/mantis/view.php?id=2205
>
> http://www.eda-stds.org/mantis/file_download.php?file_id=4489&type=bug
> <http://www.eda-stds.org/mantis/file_download.php?file_id=4489&type=bug>
>
>
>
> SVDB 2571 _x__Yes ___No
>
> http://www.eda-stds.org/mantis/view.php?id=2571
> <http://www.eda-stds.org/mantis/view.php?id=2571>
>
> http://www.eda-stds.org/mantis/file_download.php?file_id=4414&type=bug
> <http://www.eda-stds.org/mantis/file_download.php?file_id=4414&type=bug>
>
>
>
> SVDB 3035 ___Yes _x__No
>
> http://www.eda-stds.org/mantis/view.php?id=3035
> <http://www.eda-stds.org/mantis/view.php?id=3035>
>
> http://www.eda-stds.org/mantis/file_download.php?file_id=4485&type=bug
> <http://www.eda-stds.org/mantis/file_download.php?file_id=4485&type=bug>
>

Reason for no vote on 3035:

What about the following case?

     checker check(x, clk);
         logic y;
         a1: assert #0 (x);

        always @clk begin
            y <=x;
        end

     endchecker

It seems that according to this proposal, the deferred assertion would
use the current value of x, while the assignment to the checker variable
y would use the sampled value. This could create confusion.

It seems that the only way to create a truly consistent semantics is one
of two choices: either keep the current semantics: all input arguments
to a checker are sampled. Or, remove all sampling semantics from
checker arguments. Variables inside a checker would then be sampled or
not sampled according to the rules which apply everywhere else.

Tom

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