RE: [sv-ac] Call to vote. Due August 30

Hi Ben,

Reproducing the examples for convenience.

module m (input logic clock, a);

// ...

check1 c1(a, posedge clock);

check2 c2(posedge clock);

endmodule

checker check1(x, clk);

logic y;

always @clk begin

y <= x; // x is sampled

// ...

end

// ...

endchecker

checker check2(x);

logic y;

always @clk begin

y <= top.m1.a; // top.m1.a (hierarchical reference a in the module instance)

// is not sampled

// ...

end

// ...
endchecker

According to the new proposal, x is not sampled in check1, but it is sampled in y <=x, as the RHS of the checker variable assignments is sampled.
top.m1.a in check2 is also sampled for the same reason. Therefore the results are now consistent.

I think that the proposal address it, as it removes the statement about sampling checker variables, and explicitly specifies that

After substituting formal arguments by the actual arguments, all the variables on the right hand side of the assignment use the value sampled in the Preponed region of a time slot with the exception of checker variables. The current value of the checker variables is used.

Regards,
Dmitry

From: ben cohen [mailto:hdlcohen@gmail.com]
Sent: Sunday, August 29, 2010 10:41 PM
To: Korchemny, Dmitry
Cc: sv-ac@eda.org
Subject: Re: [sv-ac] Call to vote. Due August 30

SVDB 2205 __X_Yes ___No
http://www.eda-stds.org/mantis/view.php?id=2205
http://www.eda-stds.org/mantis/file_download.php?file_id=4489&type=bug

SVDB 2571 __X_Yes ___No
http://www.eda-stds.org/mantis/view.php?id=2571
http://www.eda-stds.org/mantis/file_download.php?file_id=4414&type=bug

SVDB 3035 ___Yes __X_No
http://www.eda-stds.org/mantis/view.php?id=3035
http://www.eda-stds.org/mantis/file_download.php?file_id=4485&type=bug

I need further discussions. Specifically, the pdf states:
checker check2(x);
logic y;
always @clk begin
y <= top.m1.a; // top.m1.a (hierarchical reference a in the module instance)
// is not sampled
// ...
end
// ...
endchecker
In the former case the value of the signal is sampled, whereas in the latter case it is not.
The proposed solution is not to sample checker variable arguments, but to sample the RHS of non-blocking checker variable assignments instead.
But that solution is not addressed in the changes; or is it?
Ben

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