Re: [sv-ac] Call to vote. Due August 30

SVDB 3035 _X__Yes ___No

http://www.eda-stds.org/mantis/view.php?id=3035

http://www.eda-stds.org/mantis/file_download.php?file_id=4485&type=bug

Thanks Dmitry for the clarification.

Ben

On Sun, Aug 29, 2010 at 12:41 PM, ben cohen <hdlcohen@gmail.com> wrote:

>
>> SVDB 2205 __X_Yes ___No
>>
>> http://www.eda-stds.org/mantis/view.php?id=2205
>>
>> http://www.eda-stds.org/mantis/file_download.php?file_id=4489&type=bug
>>
>>
>>
>> SVDB 2571 __X_Yes ___No
>>
>> http://www.eda-stds.org/mantis/view.php?id=2571
>>
>> http://www.eda-stds.org/mantis/file_download.php?file_id=4414&type=bug
>>
>>
>>
>> SVDB 3035 ___Yes __X_No
>>
>> http://www.eda-stds.org/mantis/view.php?id=3035
>>
>> http://www.eda-stds.org/mantis/file_download.php?file_id=4485&type=bug
>>
>
> I need further discussions. Specifically, the pdf states:
> *checker check2(x);*
> *logic y;*
> *always @clk begin*
> *y <= top.m1.a; // top.m1.a (hierarchical reference a in the module
> instance)*
> *// is not sampled*
> *// …*
> *end*
> *// …*
> *endchecker*
> *In the former case the value of the signal is sampled, whereas in the
> latter case it is not.*
> *The proposed solution is not to sample checker variable arguments, but to
> sample the RHS of non-blocking checker variable assignments instead.*
> But that solution is not addressed in the changes; or is it?
> Ben
>
>>
>>
>>
>>
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