[sv-ac] RE: Uploaded proposal for Mantis 0002804

Hi Erik,

We need allow a case when a system task is called in the procedure, e.g., inferring the clock in the following example should be legal:

always @(posedge clk) begin
  assert property(a);
 $display ("%b", clk);
end

A problem, however, remains, since a normal task may wrap a system task:

task my_display(logic sig);
  $display ("%b", clk);
endtask

always @(posedge clk) begin
  assert property(a);
 my_display (clk);
end

Thanks,
Dmitry

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Seligman, Erik
Sent: Friday, May 14, 2010 7:26 PM
To: sv-ac@eda.org
Subject: [sv-ac] Uploaded proposal for Mantis 0002804

Hi guys-I uploaded a proposal for this item related to inferring clocks for procedural concurrent assertions, at http://www.verilog.org/mantis/view.php?id=2804 . Please take a look & send comments.

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