Re: [sv-ac] SV AC feedback for the coming PAR

Hello,
  Please add:

1. Allow run time variables as cycle_delay

Thanks
Srini
www.cvcblr.com

On Fri, Feb 19, 2010 at 12:17 AM, Korchemny, Dmitry <
dmitry.korchemny@intel.com> wrote:

> Hi all,
>
>
>
> I collected the following feedback from SV-AC:
>
> · Relax restrictions imposed on checkers and support module-like
> code in checkers
>
> · Reduce restrictions on where checkers and concurrent assertions
> may be used (functions, tasks, c lasses)
>
> · Enhance assertion system functions
>
> · Enhance type system to allow generic integral type and explicit
> type compatibility check
>
> · Allow real data types in concurrent assertions. Integration with
> VerilogVMS
>
> · Introduce temporal coverage – tighter integration
>
> · Enhance concurrent assertions, including local variables
>
>
>
> Please, let me know if your requirement hasn’t been captured.
>
>
>
> Thanks,
>
> Dmitry
>
>
>
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