[sv-ac] SV AC feedback for the coming PAR

Hi all,

I collected the following feedback from SV-AC:

* Relax restrictions imposed on checkers and support module-like code in checkers

* Reduce restrictions on where checkers and concurrent assertions may be used (functions, tasks, c lasses)

* Enhance assertion system functions

* Enhance type system to allow generic integral type and explicit type compatibility check

* Allow real data types in concurrent assertions. Integration with VerilogVMS

* Introduce temporal coverage - tighter integration

* Enhance concurrent assertions, including local variables

Please, let me know if your requirement hasn't been captured.

Thanks,
Dmitry

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