RE: [sv-ac] Question on editing for Mantis 1698

From: Stuart Sutherland <stuart_at_.....>
Date: Fri Sep 05 2008 - 12:37:44 PDT
SV-AC,
 
I am still waiting for the editing instructions regarding the duplicate
example described below.  Please let me know ASAP what action to take, or if
I should just close this Mantis item and leave the duplicate example in the
LRM.
 
 
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
www.sutherland-hdl.com


 
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Korchemny, Dmitry
Sent: Tuesday, September 02, 2008 3:28 AM
To: stuart@sutherland-hdl.com; sv-ac@eda.org
Cc: Lisa Piper; Seligman, Erik
Subject: RE: [sv-ac] Question on editing for Mantis 1698
 
Is it? The only difference I could spot was the typesetting of iff in "is a
proper subexpression of posedge clock iff reset == 0." Because of it the
layout is slightly different.
 
Dmitry
 
From: Stuart Sutherland [mailto:stuart@sutherland-hdl.com] 
Sent: Tuesday, September 02, 2008 1:23 PM
To: Korchemny, Dmitry; sv-ac@eda.org
Cc: 'Lisa Piper'; Seligman, Erik
Subject: RE: [sv-ac] Question on editing for Mantis 1698
 
The example appears twice, but the explanations after the examples are
different.  Should one of the duplicate examples and its explanation be
deleted or changed?
 
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
www.sutherland-hdl.com
 
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Korchemny, Dmitry
Sent: Tuesday, September 02, 2008 2:58 AM
To: stuart@sutherland-hdl.com; sv-ac@eda.org
Cc: Lisa Piper; Seligman, Erik
Subject: RE: [sv-ac] Question on editing for Mantis 1698
 
In the subclause 16.15.5 Embedding concurrent assertions in procedural code,
the text starting with "Another, more complex example that is legal is as
follows:", and ending with
 
always @(posedge mclk) begin
#10 q <= d1; // delay prevents clock inference
@(negedge mclk) // event control prevents clock inference
#10 q1 <= !d1;
r5_p: assert property (r5); // no inferred clock
end
 
 has been inserted twice.
 
Dmitry
 
From: Stuart Sutherland [mailto:stuart@sutherland-hdl.com] 
Sent: Tuesday, September 02, 2008 12:48 PM
To: Korchemny, Dmitry; sv-ac@eda.org
Cc: 'Lisa Piper'; Seligman, Erik
Subject: RE: [sv-ac] Question on editing for Mantis 1698
 
Thanks for the clarification.  Now I know what needs to be corrected for
item 1 of bug note 7090.  What needs to be corrected to fix the duplicate
text and example indicated in item 2 of that bug note? 
 
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
www.sutherland-hdl.com
 
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Korchemny, Dmitry
Sent: Tuesday, September 02, 2008 1:12 AM
To: stuart@sutherland-hdl.com; sv-ac@eda.org
Cc: Lisa Piper; Seligman, Erik
Subject: RE: [sv-ac] Question on editing for Mantis 1698
 
Hi Stu,
 
This is only the matter of coloring: "sampled" should be deleted, while
"value" remains unchanged.
 
Regards,
Dmitry
 
From: Stuart Sutherland [mailto:stuart@sutherland-hdl.com] 
Sent: Tuesday, September 02, 2008 11:07 AM
To: Korchemny, Dmitry; sv-ac@eda.org
Cc: 'Lisa Piper'; Seligman, Erik
Subject: RE: [sv-ac] Question on editing for Mantis 1698
 
Dmitry,
 
Thanks, but I still cannot make sense out of what editing changes are
required.  As far as I can tell, the "While it should be" text you have
provided is identical to the current text.
 
It would be best to align the change instructions to the clean version of
draft 6.  The instructions need to be explicit, showing exactly what text is
being deleted or added.  Once again, do not use page numbers.  The page
numbers in the work-in-progress draft 7 do not match any previous draft.
 
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
www.sutherland-hdl.com
 
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Korchemny, Dmitry
Sent: Monday, September 01, 2008 10:45 PM
To: stuart@sutherland-hdl.com; sv-ac@eda.org
Cc: Lisa Piper; Seligman, Erik
Subject: RE: [sv-ac] Question on editing for Mantis 1698
 
Hi Stu,
 
Here is my understanding of these notes:
 
Note 7090:
 
16.9.4 Sampled value functions
Page 333 (next page after Figure 16-4-Value change expressions):
 
There is a new line after
 
expression1 and expression2 can may be any expression allowed in assertions.
If expression2 is not specified,
then it defaults to 1'b1.
 
In Draft 6. This new line is redundant.
 
Then it is written:
 
$past returns the sampled value of the expression expression1 that was
present number_of_ticks prior to the time
of evaluation of $past. sampled in the Preponed region of a particular
timestep strictly prior to the one in
which $past is evaluated.
 
While should be:
 
$past returns the sampled value of the expression expression1 that was
present number_of_ticks prior to the time
of evaluation of $past. sampled in the Preponed region of a particular
timestep strictly prior to the one in
which $past is evaluated.
 
Note 7131:
 
Same thing as the second part of 7090.
 
Regards,
Dmitry
 
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Stuart Sutherland
Sent: Tuesday, September 02, 2008 7:39 AM
To: sv-ac@server.eda.org
Subject: [sv-ac] Question on editing for Mantis 1698
 
Can someone please define the exact corrections that are needed for bug note
7090 in Mantis 1698? Please be sure to include subclause numbers.  Page
numbers are meaningless, as they change frequently.
 
Also, bug note 7131 is an observation.  Is any correction needed?
 
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
www.sutherland-hdl.com

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Received on Fri Sep 5 12:39:04 2008

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