RE: [sv-ac] Assertion action control system tasks - for assume and cover

sorry my fault assert statement is defined by lrm as assert, cover or assume
directive - so I get the answer by my self.
 
DANiel

  _____  

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Daniel Mlynek
Sent: 3 września 2008 14:47
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] Assertion action control system tasks - for assume and
cover


draft6 says Assertion action control system tasks cannot control assume and
cover actions - only assert and expect action  can be controled. This was
done deliberatelly. Why not to allow to switch off cover pass action or
assume pass or fail action? 

LRM: "SystemVerilog provides six system tasks to control the execution of
assertion action blocks for concurrent assertions that are associated with
assertion statements and the expect statement:"

 

DANiel


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