Hi Dmitry, T(e iff b) = T(e) || b Isn't the iff event control operator some kind of and? /Johan On Thu, Nov 01, 2007 at 11:49:21AM +0200, Korchemny, Dmitry wrote: > Hi all, > > > > I filed a new mantis item on edge and level sensitive clocks. The > problem is that in SystemVerilog the clocks are edge sensitive, e.g., > @clk means that clk is going to change, while in the formal semantics > description in Annex F the clocks are level-sensitive and @clk means > that clk is high. The rules of converting edge sensitive clocks to level > sensitive clocks are lacking in Annex F, and they are a subject of this > proposal. Please, have a look. > > > > Thanks, > > Dmitry > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > -- ------------------------------------------------------------ Johan Mårtensson Office: +46 31 7451913 Jasper Design Automation Mobile: +46 703749681 Arvid Hedvalls backe 4 Fax: +46 31 7451939 411 33 Gothenburg, Sweden Skype ID: johanmartensson ------------------------------------------------------------ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Nov 2 05:46:26 2007
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