RE: [sv-ac] Mantis 2168 - Formal semantics for edge-sensitive clocks

Sure,

Here is an updated version. Also updated in Mantis (under the same name).

Thanks,
Dmitry

-----Original Message-----
From: johan.martensson@jasper-da.com [mailto:johan.martensson@jasper-da.com] 
Sent: Friday, November 02, 2007 2:46 PM
To: Korchemny, Dmitry
Cc: sv-ac@eda.org
Subject: Re: [sv-ac] Mantis 2168 - Formal semantics for edge-sensitive clocks

Hi Dmitry,

T(e iff b) = T(e) || b

Isn't the iff event control operator some kind of and?

/Johan

On Thu, Nov 01, 2007 at 11:49:21AM +0200, Korchemny, Dmitry wrote:
> Hi all,
> 
>  
> 
> I filed a new mantis item on edge and level sensitive clocks. The
> problem is that in SystemVerilog the clocks are edge sensitive, e.g.,
> @clk means that clk is going to change, while in the formal semantics
> description in Annex F the clocks are level-sensitive and @clk means
> that clk is high. The rules of converting edge sensitive clocks to level
> sensitive clocks are lacking in Annex F, and they are a subject of this
> proposal. Please, have a look.
> 
>  
> 
> Thanks,
> 
> Dmitry
> 
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