[sv-ac] Mantis 2168 - Formal semantics for edge-sensitive clocks

Hi all,

 

I filed a new mantis item on edge and level sensitive clocks. The
problem is that in SystemVerilog the clocks are edge sensitive, e.g.,
@clk means that clk is going to change, while in the formal semantics
description in Annex F the clocks are level-sensitive and @clk means
that clk is high. The rules of converting edge sensitive clocks to level
sensitive clocks are lacking in Annex F, and they are a subject of this
proposal. Please, have a look.

 

Thanks,

Dmitry

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