RE: [sv-ac] updated proposal for 1641

Hi Manisha,

 

I have the following comments:

* The proposal refers to the Verilog system task $display. I think that
it should state just system task $display (without referencing to
Verilog), since we have the unified LRM for SystemVerilog

* The proposal states "Since the assertion is a statement that something
must be true, the information about assertion failure can be printed
using one of the following severity system tasks in the action block." I
think it should just state "The information about assertion failure can
be printed using one of the following severity system tasks in the
action block."

 

Thanks,

Dmitry

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Kulshrestha, Manisha
Sent: Friday, October 05, 2007 9:28 AM
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] updated proposal for 1641

 

Hi,

 

I have uploaded updated proposal for 1641. The latest proposal is
severity_tasks_7.pdf. The changes were made based on the feedback in the
mantis. The feedback was to not repeat the same information in chapter
16 as the details about the tasks were in clause 19.9. Please review the
changes and let me know your feedback.

 

Could someone forward this to sv-bc .

 

Thanks.

Manisha 


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