RE: [sv-ac] {Filename?} imply and iff operators

Doron,

I think $ is OK because it's just one of the characters
that is legal in an identifier.  So

  until$past

will parse as one token, and correctly yield a 
syntax error.  By contrast, < is an operator symbol
that (in Verilog) can divide two tokens, so 
a<b  is clearly three tokens - identifiers a and b,
and the operator <.

Putting the $ at the *end* of the name avoids any
confusion with system tasks, which always *begin*
with a $.

-- 
Jonathan Bromley, Consultant

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> -----Original Message-----
> From: Bustan, Doron [mailto:doron.bustan@intel.com]
> Sent: 17 September 2007 09:47
> To: Jonathan Bromley; sv-ac@server.eda-stds.org
> Subject: RE: [sv-ac] {Filename?} imply and iff operators
> 
> 
> Thanks Jonathan,
> 
>  I think that $ could be a problem because 
> 
> "P1 until$past(a)" could be hard to parse as well.
> 
> I am not very familiar with parsing. Does anybody who is familiar
> with SV parsing can indicate whether the <until> make parsing harder? 
> 
> We have some discussions about the <> and everybody agree 
> that they are
> not esthetic. The reason that we didn't change them is that 
> we could not
> come with a better idea.
> 
> Doron
> 
> -----Original Message-----
> From: Jonathan Bromley [mailto:jonathan.bromley@doulos.com] 
> Sent: Monday, September 17, 2007 1:31 PM
> To: Bustan, Doron; sv-ac@server.eda-stds.org
> Subject: RE: [sv-ac] {Filename?} imply and iff operators
> 
> Doron,
> 
> Although it's not really my area of expertise, I am
> very enthusiastic about your proposal to add LTL to
> SVA, so I spent some time looking at your latest
> version.  Please excuse me if I'm misunderstanding.
> 
> The strong operators <next> etc. are lexically very 
> curious.  Since < and > are regular operators, I suspect
> their existence as part of an LTL operator keyword may
> make it very difficult for compilers to issue sensible
> error diagnostics.  Given that $ is a legal character in
> Verilog identifiers, would it not be preferable to use
> "next$" instead?  Since $ already has an intuitive 
> meaning of "infinity" in SVA, I think that would be
> quite easy to read and remember.
> 
> Similarly, introducing a keyword-pair "until with" 
> seems odd to me.  Personally I have no problem with
> PSL's "until_", but I can see that it might be considered
> hard to read.
> 
> I found a couple of very trivial typos:
> - "week" for "weak"
> - "ture" for "true"
> 
> Thanks for your efforts - I think LTL would be a great
> addition to SVA.
> --
> Jonathan Bromley, Consultant
> 
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
> 
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
> 1AW, UK
> Tel: +44 (0)1425 471223                   Email:
> jonathan.bromley@doulos.com
> Fax: +44 (0)1425 471573                           Web:
> http://www.doulos.com
> 
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
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