RE: [sv-ac] arguments passing

Hi Doron,

The proposal looks OK with me (I am not addressing the issue you raised
in this mail, it requires a separate discussion), but I need some more
time to review it.
 
Here are several minor comments:

* Page 3. Need to fix fonts in the added code snippet. Also a space is
missing before "endproperty".

* In the example $var is used before introduced.

* Page 4. property_spec --> assertion

* Need to fix fonts with $var

Thanks,
Dmitry

-----Original Message-----
From: Doron Bustan [mailto:dbustan@freescale.com] 
Sent: Tuesday, June 26, 2007 12:36 AM
To: Doron Bustan
Cc: Lisa Piper; Singh, Tej; Bassam Tabbara; John Havlicek; Korchemny,
Dmitry; sv-ac@eda.org
Subject: Re: [sv-ac] arguments passing

I fix a few problems in the formal semantics rosed by Yaniv and John.

A question that need to be discussed in the meeting tomorrow is:

Should $var be applied on untyped formal arguments?

The advantage of applying $var is that in some cases it will allow 
operations
that are not allowed otherwise.  For example, consider

property p1(uf);
    uf[2];
endproperty

logic [3:0] a,b;

then

without $var, the following is not legal:

assert property (p1(a &b));

not even with explicit casting

assert property (p1((logic [3:0])'(a &b));

and $var will allow this.


The disadvantage is that the user will need to know for every 
expression, whether it has
a well defined type. This is not an easy task in system verilog and may 
cause confusion.

Doron

Doron Bustan wrote:

> I modified the formalsemantics part of the arguments passing (1549).
> I think that the recursive properties are well defined now.
>
> Doron
>

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