RE: [sv-ac] variables vs. expressions

The example in 4 is illegal, because the members of a struct, like the
properties of a class object, can only be accessed by name via an
hierarchical_identifier.  This is in contrast to the syntax for calls to
the methods of a class object, which does not require the use of an
hierarchical_tf_identifier. 

(I write 'by name' above, because members of packed structs can also be
accessed via part-selects, and members of structs and properties of
class objects can be accessed via part-selects into bit streams.)

-- Brad
 

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Doron Bustan
Sent: Wednesday, May 30, 2007 7:46 AM
To: Korchemny, Dmitry; sv-ac@eda.org
Subject: [sv-ac] variables vs. expressions

Hi,

I took an action item to review cases at SV, where there are operations
that are allowed on variables with a specific type, but are not allowed
on expressions with the same type.
Here they are:

1. sequence .matched, .trigger,  .ended

2. bit select and bit slice on vectors.

3. the methods first(), last(), next(),  prev(), num(), name() of enum
types.
    There  is no explicit language saying that these methods should not
be
     used on expression, but I think that one may conclude it from the
text.

4. I read the aggregate data types clause and the cast clause, I cannot
say
    whether the following code is legal:

    typedef struct {bit a; bit b;} AB;

    assert property((AB'(2'b10)).a ==1);

    Does anybody know?

Doron


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